1. Field of the Invention
The present invention relates to a data driver and a display apparatus for displaying a display data by using the data driver. The present invention is based on Japanese Patent Application No. 2006-330962. The disclosure of the application is incorporated herein by reference.
2. Description of Related Art
Display apparatuses such as a TFT (Thin Film Transistor) type liquid crystal display apparatus, a simple-matrix type liquid crystal display apparatus, an electroluminescence (EL) display apparatus, and a plasma display apparatus have been widely used.
As an example of a conventional display apparatus, the TFT type liquid crystal display apparatus will be described. FIG. 1 shows a configuration of the conventional TFT type liquid crystal display apparatus 101. The display apparatus 101 includes a timing controller 2, a gate driver 120, a data driver 130 and a liquid crystal panel 10.
The liquid crystal panel 10 includes a plurality of pixels 11 which are arranged on a glass substrate 3 in a matrix. For example, (m×n) pixels 11 (m and n are integers of 2 or more) are arranged on the glass substrate 3. Each of the (m×n) pixels 11 includes a thin film transistor (TFT) 12 and a pixel capacitor 15. The pixel capacitor 15 includes a pixel electrode and a counter electrode opposite to the pixel electrode. The TFT 12 includes a drain electrode 13, a source electrode 14 connected to the pixel electrode, and a gate electrode 16.
The gate driver 120 is connected to one end of m gate lines G1 to Gm. The data driver 130 is connected to one end of n data lines D1 to Dn. The m gate lines G1 to Gm are connected to the gate electrodes 16 of the TFTs 12 of the pixels 11 in m rows, respectively. The n data lines D1 to Dn are connected to the drain electrodes 13 of the TFTs 12 of the pixels 11 in n columns, respectively.
The timing controller 2 supplies a gate clock signal GCLK to the gate driver 120 to select and drive one of the gate lines in one horizontal period. Also, the timing controller 2 supplies a clock signal CLK and one-line display data DATA to the data driver 130. A data DATA for one horizontal line contains n display data corresponding to the data lines D1 to Dn.
The data driver 130 outputs the n display data to the n data lines D1 to Dn in accordance with the clock signal CLK. At this time, the TFTs 12 of (1×n) pixels 11 corresponding to the driven gate line and the n data lines D1 to D2 are turned on. Therefore, the n display data are written to the pixel capacitors 15 of the (1×n) pixels 11, which are held until a next write operation of display data. With this, the n display data are displayed as the one-line display data DATA.
The data driver 130 includes K data driver circuits 130-1 to 130-K which are cascade-connected in this order for allowing display of the n pixels. FIG. 2 shows a configuration of the data driver circuit 130. It should be noted that “K” is an integer of 2 or more, which satisfies n/y (n>y, y is an integer of 2 or more). Each of the K data driver circuits 130-1 to 130-K includes an internal signal circuit 40, a shift register circuit 131, a data register circuit 32, a latch circuit 33, a level shifter circuit 34, a digital/analog (D/A) converter circuit 35, a data output circuit 36, and a gradation voltage generating circuit 37.
The internal signal circuit 40 is connected to the shift register circuit 131. The shift register circuit 131 is connected to the data register circuit 32, and the data register circuit 32 is connected to the latch circuit 33. The latch circuit 33 is connected to the level shifter circuit 34, and the level shifter circuit 34 is connected to the D/A converter circuit 35. The D/A converter circuit 35 is connected to the data output circuit 36 and the gradation voltage generating circuit 37. Y output buffers of the data output circuit 36 are connected to y data lines D1 to Dy, respectively.
The gradation voltage generating circuit 37 includes a plurality of γ-correction resistance elements that are connected in series as shown in FIG. 3. The gradation voltage generating circuit 37 divides a difference between reference voltages from a power supply circuit (not shown) by the plurality of γ-correction resistance elements to generate a plurality of gradation voltages. For example, when a display of sixty-four gradation levels is performed, the gradation voltage generating circuit 37 divides reference voltages by sixty-three γ-correction resistance elements R0 to R62, and generates positive-polarity gradation voltages. The same is performed for negative-polarity gradation voltages.
The shift register circuit 131 includes y registers (not shown), and the data register circuit 32 includes y registers (not shown). The latch circuit 33 includes y latches (not shown), and the level shifter circuit 34 includes y level shifters (not shown).
The D/A converter circuit 35 includes y D/A converters (see FIG. 4). The y D/A converters contain a P-type converters (PchDAC) which output the positive-polarity gradation voltages and N-type converters (NchDAC) which output the negative-polarity gradation voltage. For example, of the above y D/A converters, odd-numbered D/A converters are the PchDAC, and even-numbered D/A converters are the NchDAC. The D/A converter circuit 35 further includes y switching elements (see FIG. 4) for performing an inversion drive in which the positive-polarity gradation voltage and the negative-polarity gradation voltage are alternately applied to the pixels 11. The data output circuit 36 includes y output buffers or amplifiers (see FIG. 4).
The timing controller 2 supplies the clock signal CLK to the K data driver circuits 130-1 to 130-K, supplies the one-line display data DATA to the K data driver circuits 130-1 to 130-K in one horizontal period, and supplies a shift pulse signal STH to the data driver circuit 130-1 as a start pulse signal. The data driver circuit 130-i outputs the y display data contained in the one-line display data DATA to the y data lines D1 to Dy, respectively, in response to the clock signal CLK and the shift pulse signal STH. It should be noted that “i” is an integer that satisfies 1≦i≦K.
In this case, the internal signal circuit 40 of the data driver circuit 130-1 generates a reset signal RESET and an internal shift pulse signal ISTH that is delayed by a predetermined number of clocks from the reset signal RESET, based on the shift pulse signal STH supplied from the timing controller 2, and outputs those signals to the shift register circuit 131. The y shift registers of the shift register circuit 131 of the data driver circuit 130-i (i=1, 2, . . . , K) are reset in response to the reset signal RESET (will be described later).
In the data driver circuit 130-i (in this case, i=1, 2, . . . , K-1), each of the y shift registers of the shift register circuit 131 shifts the internal shift pulse signal ISTH in order in synchronization with the clock signals CLK, and outputs the shifted signal to the y data registers of the data register circuit 32. The yth shift register of the shift register circuit 131 outputs the internal shift pulse signal ISTH to the yth data register of the data register circuit 32, and outputs it to the data driver circuit 130-(i+1) (in this case, i=1, 2, . . . , K−1). In the data driver circuit 130-K, each of the y shift registers of the shift register circuit 131 shifts the internal shift pulse signal ISTH in order in synchronization with the clock signal CLK, and outputs the shifted signal to the y data registers of the data register circuit 32.
In the data driver circuit 130-i, each of the y shift registers acquires the y display data from the timing controller 2 in synchronization with the internal shift pulse signal ISTH from the y shift registers of the shift register circuit 131, and outputs them to the y latches of the latch circuit 33. The y latches latch the y display data from the y data registers of the data register circuit 32 at a same timing, and output them to the y level shifters of the level shifter circuit 34. Each of the y level shifters performs level-conversion on the y display data, and the y level shifters output them to the y D/A converters of the D/A converter circuit 35. The y D/A converters perform a digital/analog conversion on the y display data outputted from the y level shifters of the level shifter circuit 34. For example, as shown in FIG. 4, each of the PchDACs serving as the odd-numbered (the 1st, 3rd, . . . , (y−1)th) D/A converters selects an output gradation voltage from among the positive-polarity sixty-four gradation voltages in accordance with the display data outputted from a corresponding one of the odd-numbered (the 1st, 3rd, . . . , (y−1)th) level shifters, and outputs the selected voltage to a corresponding one of the odd-numbered (the 1st, 3rd, . . . , (y-1)th) output buffers of the data output circuit 36 via a corresponding one of the odd-numbered (the 1st, 3rd, . . . , (y−1)th) switching elements. Also, each of the NchDACs serving as the even-numbered (the 2nd, 4th, . . . , yth) D/A converters selects an output gradation voltage among the negative-polarity sixty-four gradation voltages in accordance with the display data outputted from a corresponding one of the even-numbered (the 2nd, 4th, . . . , yth) level shifters, and outputs the selected voltage to a corresponding one of the even-numbered (the 2nd, 4th, . . . , yth) output buffers of the data output circuit 36 via a corresponding one of the even-numbered (the 2nd, 4th, . . . , yth) switching elements.
Meanwhile, for performing an inversion drive, as shown in FIG. 4, each of the PchDACs serving as the odd-numbered (the 1st, 3rd, . . . , (y−1)th) D/A converters selects an output gradation voltage among the positive-polarity gradation voltages of sixty-four gradations in accordance with the display data outputted from a corresponding one of the odd-numbered (the 1st, 3rd, . . . , (y−1)th) level shifters, and outputs the selected voltage to a corresponding one of the even-numbered (the 2nd, 4th, . . . , yth) output buffers of the data output circuit 36 via a corresponding one of the odd-numbered (the 1st, 3rd, . . . , (y−1)th) switching elements. Also, each of the NchDACs serving as the even-numbered (the 2nd, 4th, . . . , yth) D/A converters selects an output gradation voltage among the negative-polarity sixty-four gradation voltages in accordance with the display data outputted from a corresponding one of the even-numbered (the 2nd, 4th, . . . , yth) level shifters, and outputs the selected voltage to a corresponding one of the odd-numbered (the 1st, 3rd, . . . , (y−1)th) output buffers of the data output circuit 36 via a corresponding one of the even-numbered (the 2nd, 4th, . . . , yth) switching elements.
As such, each of the above-described y D/A converters outputs the y output gradation voltages to the y output buffers of the data output circuit 36. The y output buffers output the y display data from the D/A converter circuit 35 to the y data lines D1 to Dy.
FIG. 5 shows a configuration of the shift register circuit 131 of the data driver circuit 130-i. The shift register circuit 131 of the data driver circuit 130-i is a 32-bit shift register circuit (y=32), which includes eight 4-bit partial shift registers SR1 to SR8 which are cascade-connected in this order. As shown in FIG. 6, each of the eight partial shift registers SR1 to SR8 includes four synchronous D-type flip-flops (to be referred to as flip-flops, hereinafter) F1 to F4 which are cascade-connected in this order. Each of the four flip-flops F1 to F4 needs to be reset (initialized) then is subjected to a normal operation, since an output state thereof becomes unstable under circumstances, e.g. immediately after a supply of a power source, and immediately after the transfer direction of a bidirectional register is switched. Therefore, each of the four flip-flops F1 to F4 has a reset input (R), in addition to a clock input (C), a data input (D), and an output (Q). Each output (Q) of the four flip-flops F1 to F4 is connected to the above-described data register circuit 32.
The data input (D) of the flip-flop F1 of the partial shift register SR1 of the data driver circuit 130-1 is connected to the internal signal circuit 40 thereof, and the internal shift pulse signal ISTH is supplied thereto. The output (Q) of the flip-flop F4 of the partial shift register SRj of the data driver circuit 130-i is connected to the data input (D) of the flip-flop F1 of the partial shift register SR(j+1) of the data driver circuit 130-i. It should be noted that “j” is an integer that satisfies 1≦j≦7. The output (Q) of the flip-flop F4 of the partial shift register SR8 of the data driver circuit 130-i is connected to the data input (D) of the partial shift register SR1 of the data driver circuit 130-(i+1). Each clock input (C) of the eight partial shift registers SR1 to SR8 of the data driver circuit 130-i is connected to the timing controller 2, and the clock signal CLK is supplied thereto. Each reset input (R) of the eight partial shift registers SR1 to SR8 of the data driver circuit 130-i is connected to the internal signal circuit 40 thereof, and the reset signal RESET is supplied thereto.
Now, among the K data driver circuits 130-1 to 130-K, an operation of the shift register circuit 131 of the data driver circuit 130-1 will be described. The timing controller 2 always outputs the clock signal CLK to each of shift register circuits 131 of the K data driver circuits 130-1 to 130-K.
When resetting (initializing) the shift register circuits 131 of the K data driver circuits 130-1 to 130-K, the internal signal circuit 40 of the data driver circuit 130-1 generates the reset signal RESET and the internal shift pulse signal ISTH that is delayed by a predetermined number of clocks from the reset signal RESET based on the shift pulse signal STH supplied from the timing controller 2, and outputs those signals to the shift register circuit 131.
First, the internal signal circuit 40 of the data driver circuit 130-1 outputs the reset signal RESET to the partial shift registers SR1 to SR8 of the shift register circuit 131. The reset signal RESET is in a high level. At this time, each of the partial shift registers SR1 to SR8 is reset to an initial state in accordance with the reset signal RESET. Then, the internal signal circuit 40 of the data driver circuit 130-1 outputs the internal shift pulse signal ISTH to the flip-flop F1 of the partial shift register SR1 of the shift register circuit 131. The internal shift pulse signal ISTH is in the high level. For example, the partial shift register SRj outputs the internal shift pulse signal ISTH to the data register circuit 32 in synchronization with the clock signal CLK for four times, and outputs the internal shift pulse signal ISTH (when being synchronized with the clock signal CLK for four times) to the flip-flop F1 of the partial shift register SR(j+1). The partial shift register SR8 outputs the internal shift pulse signal ISTH outputted from the partial shift register SR7 to the data register circuit 32 in synchronization with the clock signal CLK for four times, and outputs the internal shift pulse signal ISTH (when being synchronized with the clock signal CLK for four times) to the flip-flop F1 of the partial shift register SR1 of the shift register circuit 131 of the data driver circuit 130-2. However, in the above-described data driver 130 (K data driver circuits 130-1 to 130-K), the eight partial shift registers SR1 to SR8 of the shift register circuit 131 are reset simultaneously, thereby causing following problems.
Recently, display apparatuses have been large-scaled to display the display data in a larger screen, in which the number of outputs of the display apparatus are increased. In accordance with this, the number of elements is also increased in the data driver 130. When the eight partial shift registers SR1 to SR8 as the elements operate simultaneously, an operation current (peak value) at that time increases drastically, so that a supply voltage to be supplied to the TFT type liquid crystal display apparatus 101 becomes fluctuated. This may cause malfunctions or may become a factor for generating electromagnetic noise (EMI) in some cases.
The same is true when the gate drover 120 includes the shift register circuit 131.
In conjunction with the above description, Japanese Laid Open Patent Application (JP-A-Showa 59-14195) discloses a semiconductor apparatus in which the timings of reset are shifted. This semiconductor apparatus includes a plurality of latch circuits and delay circuits. In this publication, the delay circuits delay reset signals so that the plurality of latch circuits are not reset simultaneously.
A case is discussed where the technique disclosed in Japanese Laid Open Patent Application (JP-A-Showa 59-14195) is applied to the above-described shift register circuit 131. For example, it is considered that the above delay circuit includes 8 delay sections, the 8 delay sections are connected to the eight partial shift registers SR1 to SR8, respectively, and the plurality of latch circuits are the eight partial shift registers SR1 to SR8. In this case, a delay time when the 8 delay sections delay the reset signals is referred to as 1st to 8th delay times. The 1st to 8th delay times are longer in this order. The 1st to 8th delay sections delay the reset signals by the 1st to 8th delay time, respectively, and outputs them to the partial shift registers SR1 to SR8. Each of the partial shift registers SR1 to SR8 executes a reset operation based on a corresponding one of the reset signals from the 8 delay sections.
However, in the technique disclosed in Japanese Laid Open Patent Application (JP-A-Showa 59-14195), the reset signal is not synchronized with the clock signal CLK. Thus, when the 8 delay sections output the reset signals without synchronizing with the clock signals CLK, the reset signals are outputted from the 8 delay sections at the improper timings. The partial shift registers SR1 to SR8 perform the reset at the improper timings in response to the reset signals from the 8 delay sections, respectively. Therefore, when the internal shift pulse signal ISTH is supplied to the partial shift register SR1 of the shift register circuit 131, the internal shift pulse signal ISTH is outputted from the partial shift register SR8 at an improper timing. As a result, the data register circuit 32 cannot acquire the n display data from the timing controller 2 in synchronization with the internal shift pulse signal ISTH from the shift register circuit 131.
As described, it is desired that the partial shift registers SR1 to SR8 do not perform reset operations simultaneously, while performing the reset operations in synchronization with the clock signal CLK.